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VL7722F

Product Features

· A-PHY deserializer chip, 4-channel Link, 2Gbps

· Full data rate support over Coax/STP, up to 15m

· Lower power consumption compared with currently known competing products

· QFN64 9mm x 9mm package, compatible with mainstream market chip packages

· Automotive-grade TSMC process, with cost advantages over major competitors

Specifications

A-PHY input

4-port A-PHY Receiver with independently Configurable
MIPI A-PHY standard PAL_I2C,PAL_CSI,PAL_GPIO
Support Coax/STP up to 15m at all speed
Downlink:2Gbps data rates, Uplink: 100Mbps

MIPI CSI-2
Output

C/D-PHY Combo CSI x 2 Output
D-PHY can be configured as 4+4,4+2,2+2 lanes,Up to 2.5 Gbps per lane,up to 16 virtual channels
C-PHY up to 5.7Gbps/Lane,3 lanes

I2C

Master and Slave mode 100KHz~1MHz

Clock output

Local precision CLK output

GPIOs

Up to 13 GPIOs

Peripherals

2x12C, 13xGPI0

Package

QFN56, compatible with 3rd party

Temperature

Working temperature:-40℃~105℃

Qualification

AEC-Q100 Grade 2 qualified