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VL7724S

Product Features

· A-PHY deserializer chip, 4-channel Link, 2/3.2/4/6.4/8Gbps

· Full data rate support over Coax/STP, up to 15m

· Lower power consumption compared with currently known competing products

· QFN56 8mm x 8mm package, compatible with mainstream market chip packages

· Automotive-grade TSMC process, with cost advantages over major competitors

Specifications

A-PHY input

4-port Receiver with independently Configurable
MIPI A-PHY & HSMT standard PAL_I2C,PAL_CSI, PAL_GPIO
Support Coax/STP up to 15m a all speed
Downlink:2/3.2/4/6.4/8Gbps data rates, Uplink: 100Mbps

MIPI CSI-2
Output

C/D-PHY Combo CSl x 2 Output
D-PHY can be configured as 4+4,4+2,2+2 lanes, Up to 2.5 Gbps per lane, up to 16 virtual channels
C-PHY up to 5.7Gbps/Lane, 4 lanes

I2C

Master and Slave mode 100KHz~1MHz

Clock output

Local precision CLK output

Package

QFN56, compatible with 3rd party

Temperature

Working temperature:-40℃~105℃

Qualification

AEC-Q100 Grade 2 qualified